In the past, the major concerns of the very large scale integrated (VLSI) engineers were area, performance, cost and reliability power considerations were mostly of only secondary importance. Keywords DETFF, delay, PDP, performance, power consumption, throughput. The DETFF based shift registers are simulated with different clock frequencies and the performance of the shift registers are evaluated by observing the average power, delay and PDP. As a result, power consumption is reduced, making DET flip-flops desirable for low power applications. Although the clock frequency is determined by the system specifications, the usage of DET flip-flops can reduce the clock frequency to half of its original value for the same data throughput. Double Edge Triggered Flip Flops stores data on both the rising edge and falling edge of a clock signal. This paper provides an efficient design and analysis of Serial In Serial Out (SISO), Serial In Parallel Out (SIPO), Parallel In Serial Out (PISO) and Parallel In Parallel Out (PIPO) shift registers using High Performance Double Edge Triggered D-Flip flop (DETFF). International Journal of Engineering Research & Technology (IJERT)ġII Year M.Tech, VLSI Design, Sathyabama University, Chennai.Ģ Asst.Professor, Department of ECE, Sathyabama University, Chennai.ģ Principal, Jeppiaar Institute of Technology, Kunnam, Chennai.
2GHz High Performance Double Edge Triggered D-Flip Flop Based Shift Registers In 32NM CMOS Technology
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